Execution-Driven Simulation Approach for Multiprocessor Architectures

There are three common approaches to the design of a simulator: event based approach, time based approach and the process based approach. The approach chosen when designing the model should be based on the characteristics of the system under study. One accepted approach of simulating an existing or developing architecture is trace-driven simulation. However, there are multiple problems while applying the tracedriven approach-multiprocessor simulation. For a new architecture, the order of events, the latency of the network and the number of processors might be completely different from the trace host, rendering the traces useless when evaluating timing-sensitive applications. The present paper discusses an alternative to trace driven simulation – the so-called executiondriven simulation also referred to as instruction-level simulation register-transfer simulation or cycle-by-cycle simulation. In this approach the simulator actually executes an input program allowing the development of software together with the hardware. This enables the simulator to predict the performance of a parallelized version of the program on an actual multiprocessor. In the work presented in this paper, the computational model for a tightly-coupled, asynchronous multiprocessor has been used to construct a parameterized, execution-driven multiprocessor simulator to execute parallel threads constructed from sequential programs to determine the potential speed-up on various multiprocessor configurations. The comparison between the execution-driven and trace-driven approaches provides clue that since trace-driven simulation executes faster than instruction given simulation the model used as input to the trace-driven simulation can be modified to efficiently test alternative architectural configurations.